← 返回 JSSC 论文列表JSSC 2008第6期RF & Wireless90nmPLL
A 75-GHz Phase-Locked Loop in 90-nm CMOS Technology Jri Lee Member IEEE Mingchu
90纳米CMOS工艺实现的75GHz锁相环，具有高频率操作和低参考馈通特性。
75GHz, 90nm CMOS, 1.45V, 88mW, 320MHz操作范围, <-72dBc参考边带
锁相环相位频率检测器压控振荡器参考杂散传输线
▸采用四分之三波长振荡器实现高频操作
▸基于SSB混频器的新型相位频率检测器抑制参考馈通
▸在1.45V电源下实现320MHz操作范围和低于-72dBc的参考边带
Abstract
experimental verification of a 75-GHz
phase-locked loop (PLL) fabricated in 90-nm CMOS technology is
presented. The circuit incorporates a three-quarter wavelength os-
cillator to achieve high-frequency operation and a novel phase-fre-
quency detector (PFD) based on SSB mixers to suppress the ref-
erence feedthrough. The PLL demonstrates an operation range of
320 MHz and reference sidebands of less than
72 dBc while con-
suming 88 mW from a 1.45-V supply.
Index T erms—Frequency divider, phase and