← 返回 JSSC 论文列表JSSC 2008第6期Power Management0.18μmDLLClock Generation
The Design and Analysis of a Fully Integrated Multiplying DLL With Adaptive Curr
设计并分析了一种全集成自适应电流调整的乘法DLL，用于生成低抖动时钟。
0.18μm CMOS, 1.8V, 9mW, 229.5MHz, 3.5ps rms jitter
乘法DLL频率合成器低抖动自适应电流全集成
▸自适应电流调整环路：该方法创新通过动态调整电流来优化环路性能，显著降低了时钟抖动（rms jitter仅为3.5 ps），解决了传统DLL中因固定电流导致的稳定性问题。
▸全集成环路电容：电路创新中采用完全集成的GIC（通用阻抗转换器）作为环路电容，避免了外部元件需求，节省面积（0.09 mm²），同时分析了非理想性对系统的影响。
▸离散时间模型分析：系统创新提出针对自适应电流调谐的离散时间模型，为环路稳定性提供理论支持，增强了设计可预测性，并指导了实际芯片实现。
▸低功耗设计：在0.18μm CMOS工艺下实现9 mW的低功耗（1.8V供电），结合高频输出（229.5 MHz），展现了能效与性能的平衡。
Abstract
A multiplying-DLL-based frequency synthesizer with
a fully integrated loop capacitor employs an adaptive current-ad-
justing loop to generate a low-jitter clock. The nonidealities in
the general impedance converter (GIC) which is used as the loop
capacitor are thoroughly discussed. Additionally, the discrete-time
model for the clock generator with adaptive current tuning is
presented and the analysis of the loop stability is provided. The
frequency synthesizer occupies an active area of 0.09 mm