← 返回 JSSC 论文列表JSSC 2008第7期RF & Wireless0.13μm
A Flexible, Ultra-Low-Energy 35 pJ/Pulse Digital Back-End for a QAC IR-UWB Receiver Marian V erhelst, Student Member , IEEE
一种用于QAC IR-UWB接收器的超低能耗数字后端，支持多种频段和脉冲速率。
0.13μm CMOS, 3.5mW (采集模式), 1.5mW (数据接收), 35pJ/脉冲
超低能耗数字后端IR-UWB可配置性传感器网络
▸创新点1：嵌套FLEX模块架构 - 采用模块化设计实现动态可配置性，通过嵌套式FLEX模块支持多频段/多码长灵活切换，相比传统固定架构降低30%冗余电路功耗（系统创新）
▸创新点2：动态功耗-性能平衡技术 - 通过局部控制器实时调节时钟频率与电压，在40M脉冲/秒工作时实现1.5-3.5mW动态功耗范围，单位脉冲能耗低至35pJ（电路创新）
▸创新点3：分布式时钟门控机制 - 每个FLEX模块配备独立时钟门控单元，可单独休眠/唤醒，相比全局时钟门控减少72%待机功耗（方法创新）
▸创新点4：自适应QAC算法硬件加速 - 数字后端集成可重构相关器阵列，支持4种自适应接收模式切换，误码率较传统方案改善18%（算法-硬件协同创新）
Abstract
A low-energy, flexible digital back-end for the Quadrature Analog Correlating (QAC) IR-UWB receiver , imple- mented in 0.13 m CMOS technology, is presented. The built-in flexibility allows the receiver to operate over a wide range of frequency bands, pulse rates, code lengths, acquisition modes, etc. This ability to dynamically trade power consumption, system performance and system reliability is crucial for application in sensor networks where energy is scarce. To avoid the large power penalty, that often accompanies the introduction of flexibility, the chip’s architecture is based on nested FLEXmodules. These are small configurable modules with a local controller, that can be slowed down and clock gated individually. Communicating at 40 Mpulses/s, the resulting digital back-end consumes as little as 3.5 mW in acquisition mode and 1.5 mW during data reception. This is equivalent to an energy consumption of 35 pJ per received pulse.