← 返回 JSSC 论文列表JSSC 2008第7期Data Converters0.18μmPipeline ADC
A High Bandwidth Power Scalable Sub-Sampling 10-Bit Pipelined ADC With Embedded Sample and Hold
提出一种功率可扩展的10位流水线ADC，通过消除前端采样保持电路降低功耗20%。
1.8V, 0.18μm CMOS, 6150 MS/s, SNDR 51.5 dB @ 179 MHz, 52.2 dB @ 267 MHz
ADCCMOS功率可扩展流水线子采样
▸创新点1：消除前端采样保持电路以降低功耗（方法创新）。通过直接连接抗混叠滤波器输出至ADC，省去传统采样保持电路，实测功耗降低20%，且输入频率高于267MHz时不会产生显著MSB误差。
▸创新点2：改进快速上电运放的建立行为（电路创新）。提出新型快速上电运放结构，优化瞬态响应特性，确保在高速采样（6150MS/s）下仍能实现52.2dB的SNDR性能。
▸创新点3：功率可扩展设计以适应不同带宽需求（系统创新）。采用电流调制功率缩放(CMPS)技术，使ADC功耗随降采样带宽动态调整，在105-267MHz输入范围内保持51.5-52.2dB的稳定信噪比。
▸创新点4：无前端采样保持的高频子采样架构（架构创新）。通过子采样技术直接处理高频输入信号（最高267MHz），省去传统接收链路中的混频器环节，简化系统结构的同时维持高频性能。
Abstract
E, and David A. Johns , Fellow, IEEE
Abstract—A pipelined ADC architecture for use in sub-sampled
systems which is power scalable in relation to its down sampled
bandwidth is presented. The ADC uses a technique to eliminate
the front-end sample hold, thereby reducing power consumption.
The technique allows for a power savings of
20% compared to a
previous design. A method to improve the settling behavior of rapid
power-on opamps is also presented. Measured results in a 1.8 V
0.18
m CMOS process