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Automatic Gate Biasing of an SCCMOS Power Switch Achieving Maximum Leakage Reduc
提出一种自动偏置电路,优化SCCMOS电源开关的栅极电压以最大程度降低漏电流。
65nm Bulk技术,漏电流降低两个数量级,功耗开销45nW(常温)
漏电流电源开关SCCMOS偏置时间范围电路工艺变异
▸自动寻找最优偏置电压以适应不同环境条件
▸采用65nm体硅工艺实现超过两个数量级的漏电流降低
▸提出简单方案缓解电介质电压应力,延长击穿时间
Abstract
ndre Valentian and Edith Beigné
Abstract—Power switch transistors are very effective in cutting
the leakage currents of digital circuits in a deep-freeze mode, by
de-supplying unused blocks. Among existing power switch transis-
tors, Super Cut-off CMOS (SCCMOS) is the most suited to a low
supply voltage environment since it uses a low threshold voltage
transistor. This power switch type achieves good leakage reduc-
tion results, provided that an optimal voltage is applied on its gate
in order to