JSSC 2008第8期Clocking & PLLs0.13μm CMOSVCOCDR

A 25 Gbs Run-Length-Tolerant Burst-Mode CDR Based on a 18th-Rate Dual Pulse Ring

提出一种基于18分频双脉冲环路的25Gbps容忍长连零的突发模式时钟数据恢复电路

2.5Gb/s, 72bits长连零容忍, 42mW@1.2V, 2.7ps抖动

突发模式CDR双脉冲环路相位锁定长连零容忍无源光网络

▸采用1/8分频双脉冲独立相位控制环形振荡器

▸通过脉冲删除与重插入实现相位跟踪

▸共享环形结构消除频率失配

Abstract

IEEE Abstract—A 2.5 Gb/s burst-mode clock and data recovery (CDR) circuit is presented that uses a 1/8th-rate ring oscillator with two pulses running simultaneously that are phase independent. One “tune” pulse sets the delay of the ring by phase locking it to a ref- erence. The other “clock” pulse tracks the phase of the incoming data by a process of pulse removal and reinsertion. Because both pulses share the same ring, there is no frequency mismatch between the incoming data stream and the rec