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A High-Throughput Maximum a Posteriori Probability Detector Ruwan Ratnayake Memb
提出一种基于前向算法的高吞吐量最大后验概率检测器，适用于高速通信系统。
0.13μm CMOS, 750 Mb/s, 2.4 W
最大后验概率检测器高吞吐量Turbo处理深度流水线VLSI
▸创新点1：采用深度流水线架构，显著提升吞吐量至750 Mb/s，同时保持低功耗2.4 W，优化了系统性能。
▸创新点2：优化算法和电路设计，结合前向算法和MAP检测，提高比特误码率（BER）性能，接近信道容量极限。
▸创新点3：支持Turbo处理的迭代检测，增强接收机的信号处理能力，适用于高密度磁存储系统，有效应对ISI和SNR下降。
▸创新点4：采用0.13微米CMOS技术实现16状态EEPR4信道检测器，核心面积仅为7.1 mm²，提升了集成度和能效。
Abstract
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Abstract—This paper presents a maximum a posteriori proba-
bility (MAP) detector , based on a forward-only algorithm that can
achieve high throughputs. The MAP algorithm is optimal in terms
of bit error rate (BER) performance and, with Turbo processing,
can approach performance close to the channel capacity limit.
The implementation benefits from optimizations performed at
both algorithm and circuit level. The proposed detector utilizes
a deep-pipelined architecture implemented in skew-toleran