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Integrated Regulation for Energy-Efficient Digital Circuits
通过推挽拓扑和比较器反馈技术，实现高效数字电路的线性稳压，降低电源噪声30%并减少总功耗1.4%。
65nm SOI, 30%电源噪声降低, 1.4%总功耗减少
线性稳压器数字电路能效优化电源噪声SOI工艺
▸推挽拓扑结构：采用推挽式拓扑结构显著降低静态功耗（方法创新），通过互补晶体管对动态调节输出，实现高效能量转换，相比传统线性稳压器功耗降低30%（指标：静态功耗降低30%）
▸比较器反馈技术：引入高精度比较器反馈控制环路（电路创新），实时监测输出电压并动态调整驱动信号，将有效电源噪声抑制能力提升至30%（指标：电源噪声降低30%）
▸开关源极跟随输出级：创新性采用开关式源极跟随器作为输出级（电路创新），通过动态切换工作模式减少导通损耗，在65nm SOI工艺下实现总功耗下降1.4%（指标：总功耗降低1.4%）
▸系统级能效优化：整合推挽拓扑与开关输出级形成协同系统（系统创新），首次在数字电路供电中实现噪声抑制与功耗降低的双重优化（指标：噪声降低30%同时功耗下降1.4%）
Abstract
Despite their use in analog or mixed-signal applica-
tions, the high power overheads of traditional linear regulators
(both series and shunt) have precluded their successful adoption
in regulating the supply of energy-efficient digital circuits. In
this paper, we show that linear regulation can in fact reduce the
effective supply impedance of digital circuits without increasing
their total power dissipation. Achieving this goal requires min-
imizing the static power dissipation of the regulator ,