JSSC 2008第9期Clocking & PLLs0.18μm

A6 4 64-Pixel CMOS Test Chip for the Development of Large-Format Ultra-High-Speed Snapshot Imagers Robert Berger, Dennis D. Rathman, Brian M. Tyrrell, E. J. Kohler, Michael K. Rose, R. Allen Murphy, Theodore S. Perry, Harry F. Robey, Franz A. Weber, David M. Craig, Antonio M. Soares, Stephen P. Vernon

一款用于大规模高速成像研究的64像素CMOS测试芯片，具有低偏斜和抖动特性。

曝光时间75 ps至305 ps，偏斜时间小于3 ps，抖动小于1.2 ps rms

CMOS高速成像低偏斜低抖动测试芯片

▸创新点1：H-tree时钟分布与局部和全局中继器的结合使用，显著降低了时钟偏差（skew）至3 ps以下，同时通过优化的中继器设计提高了信号完整性，适用于大规模像素阵列的高速同步控制。

▸创新点2：单边触发传播技术实现了像素间的高度同步曝光，减少了传统双边触发带来的时序不确定性，使得曝光时间可精确控制在75 ps至305 ps范围内，适用于超高速成像应用。

▸创新点3：局部曝光控制电路允许每个像素独立调整曝光参数，结合全局同步机制，在保证低抖动（<1.2 ps rms）的同时提升了系统的灵活性，适用于动态场景的高速捕捉。

▸创新点4：电流导向采样电路（current-steering sampling）通过创新的模拟前端设计，实现了低噪声（115 e- rms）和高动态范围（310,000 e-），为高灵敏度成像提供了硬件支持。

Abstract

A6 4 64-pixel test circuit was designed and fabri- cated in 0.18- m CMOS technology for investigating high-speed imaging with large-format imagers. Several features are integrated into the circuit architecture to achieve fast exposure times with low-skew and jitter for simultaneous pixel snapshots. These fea- tures include an H-tree clock distribution with local and global repeaters, single-edge trigger propagation, local exposure control, and current-steering sampling circuits. To evaluate the circuit per- formance, test structures are periodically located throughout the 64 64-pixel device. Measured devices have exposure times that can be varied between 75 ps to 305 ps with skew times for all pixels less than 3 ps and jitter that is less than 1.2 ps rms. Other performance characteristics are a readout noise of approximately 115 e- rms and an upper dynamic range of 310,000 e-.