← 返回 JSSC 论文列表JSSC 2008第9期Power Management0.13μm CMOSPLL
A 04 ps-RMS-Jitter 13 GHz Ring-Oscillator PLL Using Phase-Noise Preamplification
提出一种低抖动环形振荡器PLL设计，采用相位噪声预放大技术
0.4 ps rms抖动, 13 GHz, 23 mW功耗, 0.07 mm²面积
锁相环环形振荡器相位噪声时钟倍频器低抖动
▸基于采样复位相位-电压转换器的新型环路滤波器结构
▸相位噪声预放大技术降低PLL带内噪声
▸可编程相位噪声和功耗的环形振荡器VCO
Abstract
This paper presents the design and experimental re-
sults of a 0.4 ps rms jitter (integrated from 3 kHz to 300 MHz offset
at 2.5 GHz) 1–3 GHz tunable ring-oscillator PLL for integrated
clock multiplier applications. A new loop filter structure based
on a sample-reset phase-to-voltage converter and a Gm-C filter
decouples reference spur performance from charge-pump current
matching and loop filter leakage, while enables phase error pream-
plification to lower PLL in-band noise without reducing VCO
an