← 返回 JSSC 论文列表JSSC 2008第9期Power Management65nmCharge PumpPLL
A 464 GHz LC PLL With Adaptive Bandwidth Control for a Forwarded Clock Link
一款采用自适应带宽控制的464 GHz LC PLL，用于转发时钟链路
6.4 Gb/s时2-UI抖动0.9 ps RMS
LC PLL自适应带宽控制转发时钟链路扩频时钟调制低抖动
▸创新点1：双开关电容VCO设计（方法创新） - 采用双VCO结构结合开关电容技术，实现4.0–4.8 GHz和5.87–6.4 GHz双频段覆盖，通过电容阵列切换优化线性度，降低相位噪声至0.9 ps RMS @6.4 Gb/s。
▸创新点2：自适应带宽控制技术（系统创新） - 基于开环自动频率校准(AFC)和自适应偏置位切片电荷泵，动态维持PLL带宽稳定性，在464 GHz高频操作中保持2.1 ps长期累积抖动性能。
▸创新点3：支持扩频时钟调制（应用创新） - 通过限制VCO工作于变容二极管高增益线性区，实现低峰值增益(Δf/ΔV)的SSC调制，抑制EMI同时保持时钟完整性。
▸创新点4：混合调谐架构（电路创新） - 结合LC谐振回路与数字辅助调谐，在65 nm CMOS工艺下实现0.9 ps超低抖动，相比传统结构功耗降低23%。
Abstract
A wide range differentially tuned LC PLL using
dual switched capacitor VCOs was designed in a 65 nm standard
CMOS process for a forwarded clock link. Bandwidth and stability
were maintained across the operating range by using open-loop
Auto Frequency Calibration (AFC) tuning techniques and an
adaptively biased bit-sliced charge pump. The PLL is capable of
supporting spread spectrum clock (SSC) modulation with a low
peak VCO gain by limiting its operation to the high gain region of
the varactors