← 返回 JSSC 论文列表JSSC 2008第9期Data Converters0.13μm CMOSFlash ADCNeural Network Accelerator
A 6-Bit 16-GSs Low-Power Wideband Flash ADC Converter in 013-22m CMOS Technology
提出一种新型终止技术，降低闪存ADC的输入电容和功耗。
6-bit, 1.6GS/s, 30dB SNDR, 800MHz ERBW, 180mW
闪存ADC终止技术低功耗宽带前置放大器
▸新型终止技术消除虚设前置放大器的过压裕度
▸降低ADC的输入电容和功耗
▸应用于6位1.6GS/s闪存ADC设计
Abstract
In this work, a new termination technique for the
averaging network of the flash analog-to-digital converter (ADC)
input preamplifiers is devised. The proposed technique eliminates
the over-range voltage headroom consumed by the dummy pream-
plifiers and therefore, the input capacitance and power dissipation
of the ADC is reduced. This technique is applied to the design
of a 6-bit 1.6-GS/s flash ADC in 0.13-
m CMOS technology.
The measured peak INL and DNL are 0.42 LSB and 0.49 LSB,
respectively. Th