A Methodology for Fast VSWR Protection Implemented in a Monolithic 3-W 55% PAE RF CMOS Power Amplifier

Abstract

In this paper, the protection of CMOS power ampli- fiers against load mismatch is addressed. To this purpose, a closed- loop protection circuit is proposed, which is based on a novel cur- rent-mode detection and comparison technique. The circuit allows a faster protection lock-in, by enabling peak detection and loop fre- quency compensation to be performed at the same circuit node, thus reducing the number of low-frequency poles and improving loop bandwidth. The effectiveness of the method is demonstrated through the implementation of a monolithic 0.25- m 2-V CMOS power ampli- fier for GSM applications, which can deliver a 3-W output power with 55% overall PAE. The amplifier is able to sustain a 20:1 load VSWR at full power. Excellent RF performance and VSWR ruggedness are hence attained simultaneously, despite a simple common-emitter power stage is used. An experimental reliability assessment allowed the cognizant choice of the maximum drain-gate stress that could be tolerated. Device degradation was characterized by operating a power gain cell at RF, under real-world load and power conditions. Analysis of the degradation data enabled the design of an efficient, yet provably reliable, power amplifier.