A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses

Abstract

A 2-port SRAM cell has to guarantee stability against simultaneously read and write (R/W)-disturbed accesses while keeping cell current (Icell). We verified that it was difficult to provide the stability without any decrease in Icell and any increase in the cell-area penalty only by using the previously proposed techniques for a 1-port cell, and have proposed a new cell biasing technique that controlled the level of the cell VSS (VSSM) with a dual-Vdd and a reduced write-bit-line (WBL) precharge scheme for an 8-transistor (8T) 2-port cell to address the above issue. In this paper, a further consideration was newly demonstrated about the stability for a 2-port SRAM under the random fluctu- ation of the threshold-voltage (Vth) in 65-nm CMOS technology. The stability with the proposed biasing was compared with that of the conventional cell-Vdd (VDDM) control for write assist [5], [6]. The results under 4- random-Vth fluctuation verified that the minimum Icell at a simultaneously R/W-disturbed cell increased by 2.4 times at Vdd /61/48 /57/86while improving the write margin (WRTM). The cell size based on the same Icell was re- duced by 20%. The minimum static noise margin (SNM) was also improved by 44%. Each stability also had the tolerance against 6- random-Vth fluctuation. Furthermore, we have challenged to apply the proposed cell biasing to a 7-transistor (7T) 2-port cell design for area saving with a unique write-assist scheme. The cell size was reduced by 26% with the 7T cell compa