JSSC 2008第9期Memory65nmSRAM

A Stable 2-Port SRAM Cell Design Against Simultaneously ReadWrite-Disturbed Acce

提出一种新型双端口SRAM单元设计，提升读写干扰下的稳定性并减小面积。

65nm CMOS, 2.4倍最小Icell提升, 20%单元面积减小, 44%静态噪声容限提升

双端口SRAM读写干扰单元偏置静态噪声容限7T单元

▸创新点1：新型单元偏置技术控制VSSM（方法创新）。通过动态调节SRAM单元的VSSM电平，有效提升了同时读写干扰下的稳定性，实验证明在65nm CMOS工艺下，最小单元电流（Icell）提升了2.4倍，静态噪声容限（SNM）改善44%。

▸创新点2：双Vdd和减少写位线预充电方案（电路创新）。采用双电源电压（Vdd）架构结合优化的写位线预充电策略，在保证单元电流（Icell）不降低的前提下，显著降低写入干扰，写入容限（WRTM）得到提升，且单元面积减少20%。

▸创新点3：7T双端口单元设计（结构创新）。将提出的偏置技术扩展至7晶体管（7T）单元结构，通过独特的写入辅助方案实现面积优化，相比传统8T单元面积减少26%，同时保持稳定性要求。

▸创新点4：抗阈值电压随机波动设计（可靠性创新）。通过理论分析和实验验证，证明所提技术在65nm工艺下对6σ阈值电压（Vth）波动具有鲁棒性，为工艺变异下的SRAM稳定性提供新解决方案。

Abstract

A 2-port SRAM cell has to guarantee stability against simultaneously read and write (R/W)-disturbed accesses while keeping cell current (Icell). We veriﬁed that it was difﬁcult to provide the stability without any decrease in Icell and any increase in the cell-area penalty only by using the previously proposed techniques for a 1-port cell, and have proposed a new cell biasing technique that controlled the level of the cell VSS (VSSM) with a dual-Vdd and a reduced write-bit-line (WBL) precharge s