Design Optimization for Integrated Neural

Abstract

Power and chip area are the most important param- eters in designing a neural recording system in vivo. This paper reports a design methodology for an optimized integrated neural recording system. Electrode noise is considered in determining the ADC’s resolution to prevent over-design of the ADC, which leads to unnecessary power consumption and chip area. The optimal transconductance and gain of the pre-amplifiers, which minimizes the power–area product of the amplifier, are mathematically derived. A numerical example using actual circuit parameters is shown to demonstrate the design methodology. A tradeoff between the power consumption of the system and the chip area in terms of the multiplexing ratio is investigated and the optimal number of channels per ADC is selected to achieve the minimum power–area product for the entire system. Following the proposed design methodology, a chip has been designed in 0.35 m CMOS process, with the multiplexing ratio of 16:1, resulting in total chip area of 2.5 mm 2.0 mm and power consumption of 5.3 mW from 1.65 V.