← 返回 JSSC 论文列表JSSC 2008第9期Data Converters0.35μmNeural Interface
Design Optimization for Integrated Neural Recording Systems
提出一种优化集成神经记录系统设计的方法,重点考虑功耗和芯片面积。
0.35μm CMOS, 1.65V, 5.3mW
神经记录系统功耗优化芯片面积ADC设计前置放大器
▸考虑电极噪声确定ADC分辨率以避免过度设计
▸数学推导前置放大器的最佳跨导和增益以最小化功耗-面积积
▸研究多路复用比例对系统功耗和芯片面积的权衡
Abstract
Power and chip area are the most important param-
eters in designing a neural recording system in vivo. This paper
reports a design methodology for an optimized integrated neural
recording system. Electrode noise is considered in determining the
ADC’s resolution to prevent over-design of the ADC, which leads
to unnecessary power consumption and chip area. The optimal
transconductance and gain of the pre-amplifiers, which minimizes
the power–area product of the amplifier, are mathematically
derived