← 返回 JSSC 论文列表JSSC 2008第9期RF & Wireless90-nm CMOSPAM-4
Design and Comparison of Three 20-Gbs Backplane Transceivers for Duobinary PAM4
研究比较了三种20Gbps背板收发器的性能，包括双二进制、PAM4和NRZ信号格式。
20-Gb/s PRBS数据，40-cm Rogers和10-cm FR4通道
背板收发器双二进制PAM4NRZCMOS
▸创新点1：系统创新 - 首次全面比较了双二进制、PAM4和NRZ三种信号格式在20 Gb/s速率下的性能，为高速背板通信提供了数据格式选择依据。
▸创新点2：电路创新 - 针对三种信号格式分别优化设计了收发器电路，采用90nm CMOS工艺实现，在40cm Rogers和10cm FR4通道上实现了20 Gb/s无差错传输。
▸创新点3：方法创新 - 提出了一种新的测试方法，通过在Rogers和FR4两种不同材质的PCB板上进行测试，评估了三种收发器在实际应用环境中的性能差异。
▸创新点4：性能创新 - 实验结果表明，在20 Gb/s速率下，NRZ信号格式仍能保持最佳性能，为高速通信系统设计提供了重要参考。
Abstract
A full study of three data formats including duobi-
nary, PAM4, and NRZ is proposed to estimate the performance
of the corresponding transceivers under different conditions.
Transceiver prototypes designed and optimized for the three sig-
nalings are presented to evaluate their performance as well as the
feasibility. The three transceivers have been tested thoroughly in
Rogers and FR4 boards. Fabricated in 90-nm CMOS technology,
all three transceivers achieve error-free operation with 20-Gb/s
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