← 返回 JSSC 论文列表JSSC 2008第9期RF & Wireless0.13μm/0.18μmCDREqualizer
Edge and Data Adaptive Equalization of Serial-Link Transceivers
提出一种补偿数据和边缘样本的自适应均衡器,改善串行链路性能。
0.13μm/0.18μm CMOS, 3.6Gb/s, BER<10^-12, 120" FR4信道
串行链路均衡器符号间干扰时钟数据恢复自适应算法
▸前向FIR均衡器和DFE补偿数据及边缘样本
▸改进的LMS算法实现均衡器自适应收敛
▸显著降低边缘ISI和抖动
Abstract
Limited channel bandwidth introduces inter-symbol interference (ISI) at both data and edge samples. In addition to the ISI at data samples, ISI at the edge samples (edge ISI) increases the bit error rate (BER) by degrading on the eye diagram and in- creasing the jitter of the clock and data recovery (CDR). This work proposes a forward FIR equalizer and a decision-feedback equal- izer (DFE) that compensate for both data and edge samples. To adapt both the data and edge equalizers, a modified LMS adapta- tion algorithm is introduced to achieve convergence. A transmitter and receiver are implemented in 0.13 m and 0.18 m technolo- gies respectively. The edge ISI is improved by 20% and the jitter is improved by 10% in measurement. The link operates over a 120 FR4 channel with 24 dB attenuation at Nyquist frequency, and the BER is below /49/48 /49/52at 3.6 Gb/s.