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JSSC 2008第9期mm-Wave65nm

Millimeter-Wave Integrated Circuits in 65-nm CMOS

65纳米CMOS工艺下毫米波集成电路的设计与测量
40GHz放大器增益14.3dB, 60GHz放大器噪声系数5.6dB, 混频器转换损耗12.5dB
毫米波CMOS集成电路放大器混频器
40GHz放大器实现14.3dB增益
60GHz放大器噪声系数5.6dB
平衡电阻混频器转换损耗12.5dB
Abstract
We present the design and measurement results of millimeter-wave integrated circuits implemented in 65-nm base- line CMOS. Both active and passive test structures were measured. In addition, we present the design of an on-chip spiral balun and the transition from CPW to the balun and report transistor noise parameter measurement results at V-band. Finally, the design and measurement results of two amplifiers and a balanced resistive mixer are presented. The 40-GHz amplifier exhibits 14.3 dB of gain and the 1-dB output compression point is at /436-dBm power level using a 1.2 V supply with a compact chip area of 0.286 mm/50. The 60-GHz amplifier achieves a measured noise figure of 5.6 dB at 60 GHz. The AM/AM and AM/PM results show a saturated output power of /437 dBm using a 1.2 V supply. In downconversion, the balanced resistive mixer achieves 12.5 dB of conversion loss and /435 dBm of 1-dB input compression point. In upconversion, the measured conversion loss was 13.5 dB with 19 dBm of 1-dB output compression point.