JSSC 2008第10期Clocking & PLLs0.18μmCDR

A 622-Mbs Mixed-Mode BPSK Demodulator Using a Half-Rate Bang-Bang Phase Detector

提出一种新型混合模式BPSK解调器，适用于家庭网络CATV线路。

0.18-μm CMOS, 1.8V, 622-Mb/s

BPSK解调器Bang-Bang相位检测器CATV家庭网络622-Mb/s

▸使用半速率Bang-Bang相位检测器

▸适用于CATV线路的家庭网络应用

▸622-Mb/s高速数据传输

Abstract

A new mixed-mode binary phase shift keying (BPSK) demodulator is demonstrated using a half-rate bang-bang phase detector commonly used in clock and data recovery (CDR) appli- cations. This demodulator can be used for new home networking applications using already installed CATV lines. A prototype chip realized by 0.18- m CMOS process can demodulate 622-Mb/s data at 1.4-GHz carrier frequency. At this data rate, the demodulator core consumes 27.5 mW from a 1.8 V power supply while the core chip ar