← 返回 JSSC 论文列表JSSC 2008第10期RF & Wireless0.12μm SiGe BiCMOSPhased Array
Single-Ended and Differential Ka-Band BiCMOS Phased Array Front-Ends
开发了Ka波段单端和差分相控阵前端，采用0.12μm SiGe BiCMOS工艺。
22.5°相位分辨率, 4° rms相位误差, 11 mW功耗, 3.4 dB噪声系数
Ka波段相控阵SiGe BiCMOS低噪声放大器相位器
▸创新点1：CMOS开关延迟网络相位器（电路创新）：采用CMOS开关延迟网络实现相位器，具有22.5°的相位分辨率和±4°的均方根相位误差，支持高达+10 dBm的射频功率，IIIp3达到+21 dBm，显著提升了Ka波段相位器的精度和线性度。
▸创新点2：SiGe低噪声放大器（电路创新）：在CMOS相位器前集成SiGe低噪声放大器，实现11±1.5 dB的增益和3.4 dB的噪声系数，功耗仅为11 mW，优化了前端系统的噪声性能和能效。
▸创新点3：差分可变增益LNA（电路创新）：开发差分可变增益低噪声放大器，支持9-20 dB的增益范围，八个增益状态下的相位不平衡度仅为±1°，功耗33 mW，增益变化控制在9.1±0.45 dB，提升了系统的灵活性和一致性。
▸创新点4：小型化芯片设计（系统创新）：单端和差分前端芯片面积分别为350×800 μm²和350×950 μm²（不包括焊盘），显著缩小了芯片尺寸，为低成本毫米波相控阵前端提供了硅基解决方案，与GaAs和InP设计竞争。
Abstract
Single-ended and differential phased array front-ends are developed for Ka-band applications using a 0.12 m SiGe BiCMOS process. The phase shifters are based on CMOS switched delay networks and have 22.5 phase resolution and 4 rms phase error at 35 GHz, and can handle /4310 dBm of RF power /40 /49/100/66/41with a 3rd order intermodulation intercept point (IIP3) of /4321 dBm. For the single-ended design, a SiGe low noise amplifier is placed before the CMOS phase shifter, and the LNA/phase shifter results in 11 1.5 dB gain and 3.4 dB of noise figure (NF), for a total power consumption of only 11 mW. For the differ- ential front-end, a variable gain LNA is also developed and shows 9-20 dB gain and 1 rms phase imbalance between the eight different gain states. The differential variable gain LNA/phase shifter consumes 33 mW, and results in 10 1.3 dB gain and 3.8 dB of NF. The gain variation is reduced to 9.1 0.45 dB with the variable gain function applied. The single-ended and differential front-ends occupy a small chip area, with a size of 350 800 m/50 and 350 950 m/50, respectively, excluding pads. These chips are competitive with GaAs and InP designs, and are building blocks for low-cost millimeter-wave phased array front-ends based on silicon technology.