← 返回 JSSC 论文列表JSSC 2008第11期RF & Wireless90nmEqualizer
A 40 Gbs CMOS Serial-Link Receiver With Adaptive Equalization and ClockData Reco
一款40 Gb/s CMOS串行链路接收器，具有自适应均衡和时钟数据恢复功能。
90nm CMOS, 115mW功耗, 40Gb/s速率, 4m电缆补偿, 10dB@20GHz损耗
时钟数据恢复均衡器40Gb/s接收器串行链路CMOS
▸采用并行路径均衡滤波器补偿铜缆高频损耗
▸仅通过调节高通路径增益实现自适应均衡
▸全速率bang-bang相位检测器仅需五个锁存器
Abstract
and Shen-Iuan Liu , Senior Member , IEEE
Abstract—This paper presents a 40 Gb/s serial-link receiver
including an adaptive equalizer and a CDR circuit. A parallel-path
equalizing filter is used to compensate the high-frequency loss in
copper cables. The adaptation is performed by only varying the
gain in the high-pass path, which allows a single loop for proper
control and completely removes the RC filters used for separately
extracting the high- and low-frequency contents of the signal.
A full-ra