← 返回 JSSC 论文列表JSSC 2008第11期Power Management0.35μm CMOSEqualizer
A CMOS 1 Gbs 5-Tap Fractionally-Spaced Equalizer David Hernandez-Garduno and Jos
设计了一种1 Gb/s 5抽头分数间隔均衡器，用于CAT5e电缆的信号均衡。
1 Gb/s, 500 ps可调群延迟, 600 MHz带宽, 58%眼图垂直开口提升
均衡器分数间隔CMOS宽带求和信号均衡
▸创新点1：基于三阶线性相位双端接段的T/2延迟线设计，通过优化群延迟调谐至500 ps且波纹小于10%，实现高频稳定性（带宽>600 MHz），解决了传统延迟线在Gb/s速率下的信号失真问题。
▸创新点2：采用跨阻转换器的宽带求和电路架构，相比传统电阻负载模拟加法器，带宽提升3.6倍，显著增强高速信号处理的线性度和频率响应特性。
▸创新点3：横向均衡器系统级创新，通过5抽头分数间隔结构（T/2）和CMOS 0.35μm工艺集成，在23米CAT5e电缆上实现1 Gb/s数据传输，眼图垂直开口率从0%提升至58%。
▸创新点4：低功耗设计创新，在26 mm²面积内仅消耗32 mA电流，通过动态偏置和电流复用技术优化能效比，适用于长距离通信场景。
Abstract
This paper presents the design of a 1 Gb/s 5-tap T/2
fractionally-spaced equalizer. The T/2 delay lines are based on
third-order linear-phase double terminated sections that offer a
tunable group delay of 500 ps with less than 10% ripple and a 3 dB
bandwidth greater than 600 MHz. Furthermore, the equalizer
architecture introduces a broadband summing circuit using a
transimpedance
converter that increases the bandwidth by
a factor of 3.6 over a conventional resistive loaded analog adder.
The topo