← 返回 JSSC 论文列表JSSC 2008第12期Power Management0.13μmTDCClock Generation
A Low-Noise Wide-BW 3.6-GHz Digital /1/6 Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization
一款低噪声宽带3.6GHz数字分数-N频率合成器，采用门控环形振荡器时间数字转换器实现高分辨率
0.13μm CMOS, 39mW功耗, 300fs积分相位噪声
频率合成器低噪声数字分数-N时间数字转换器CMOS
▸创新点1：门控环形振荡器时间数字转换器（TDC）采用6皮秒原始分辨率，结合一阶噪声整形技术，显著降低了量化噪声，实现了300飞秒以下的积分相位噪声（1 kHz至40 MHz）。这是电路创新。
▸创新点2：数字量化噪声消除技术通过数字信号处理有效抑制了TDC引入的量化噪声，提升了频率合成器的整体相位噪声性能，达到-108 dBc/Hz @ 400 kHz和-150 dBc/Hz @ 20 MHz。这是方法创新。
▸创新点3：异步分频器设计避免了分频值延迟变化，提高了输出频率的稳定性和精度，增强了系统的可靠性。这是电路创新。
▸创新点4：采用10位50 MHz被动式数模转换器（DAC）实现振荡器的数字控制，简化了模拟电路设计，同时降低了功耗和面积。这是系统创新。
Abstract
A 3.6-GHz digital fractional-N frequency synthesizer achieving low noise and 500-kHz bandwidth is presented. This architecture uses a gated-ring-oscillator time-to-digital converter (TDC) with 6-ps raw resolution and first-order shaping of its quantization noise along with digital quantization noise cancella- tion to achieve integrated phase noise of less than 300 fs (1 kHz to 40 MHz). The synthesizer includes two 10-bit 50-MHz passive digital-to-analog converters for digital control of the oscillator and an asynchronous frequency divider that avoids divide-value delay variation at its output. Implemented in a 0.13- m CMOS process, the prototype occupies 0.95-mm /50active area and dis- sipates 39 mW for the core parts with another 8 mW for the oscillator output buffer. Measured phase noise at 3.67 GHz carrier frequency is 108 and 150 dBc/Hz at 400 kHz and 20 MHz offset, respectively.