JSSC 2008第12期Data Converters0.18μm CMOSDelta-Sigma ADC

A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, 98 dB THD, and 79 dB SNDR Kyehyung Lee, Student Member , IEEE, Jeongseok Chae , Student Member , IEEE, Mitsuru Aniya

该论文提出了一种结合噪声耦合和时间交织技术的宽带高线性度ADC，实现了42 MHz带宽和98 dB THD。

1.5 V电源, 4.2 MHz信号带宽, 79 dB SNDR

噪声耦合时间交织Delta-Sigma ADC高线性度宽带

▸创新点1：噪声耦合技术通过通道间耦合显著提升噪声整形环路阶数（方法创新），该技术在不增加硬件复杂度的前提下，将有效噪声整形阶数提高至传统结构的2倍以上，实测THD达到98 dB

▸创新点2：时间交织架构与噪声耦合的协同设计（系统创新），通过双通道交织采样不仅扩展带宽至42 MHz，还放大了噪声耦合效应，使4.2 MHz带宽内SNDR达到79 dB

▸创新点3：创新的多环路音调抑制机制（电路创新），利用噪声耦合的随机化特性消除Delta-Sigma调制器固有的极限环振荡，在0.18μm CMOS工艺下实现无音调干扰的纯净频谱

▸创新点4：低压高线性度设计（电路创新），在1.5V电源电压下通过优化开关时序和反馈系数，同时实现100 dB动态范围和98 dB THD，突破传统低压ADC的线性度瓶颈

Abstract

This paper describes a wideband high-linearity /1/6 ADC. It uses noise coupling combined with time interleaving. Two versions of a two-channel time-interleaved noise-coupled /1/6 ADC were realized in a 0.18- m CMOS technology. Noise coupling between the channels increases the effective order of the noise-shaping loops, provides dithering, and prevents tone generation in all loops. Time interleaving enhances the effects of noise coupling. Using a 1.5 V supply, the device achieved excellent linearity ( /83/70/68/82 100 dB, /84/72/68 /61 98 dB) and an SNDR of 79 dB in a 4.2 MHz signal band.