JSSC 2008第12期Data Converters65nmSAR ADC

Highly Interleaved 5-bit 250-MSamples 12-mW ADC With Redundant Channels in 65-nm

65nm工艺下36路交织5位250MS/s ADC，采用冗余通道提高良率至88%。

5-bit 250MS/s, 28.4dB SNDR@Nyquist, 1.20mW@800mV

ADC时间交织冗余设计低功耗SAR

▸创新点1：采用36路时间交织技术（Time-interleaving）结合800mV低核心电压，在保持250MS/s高速采样率的同时实现12mW超低功耗，通过并行慢速电路降低单位转换能耗，属于系统级能效创新

▸创新点2：引入6个冗余通道（17%面积开销）的容错设计，将芯片良率从42%提升至88%，通过硬件冗余补偿深亚微米工艺下的局部变异影响，属于制造可靠性创新

▸创新点3：时钟分区架构（Clock partitioning）将高速采样时钟仅分布在3个中央采样网络，其余区域采用低频时钟分发，减少89%高速时钟网络功耗，属于时钟树优化创新

▸创新点4：抗偏移全局顶板采样网络（Skew-resistant global top-plate）支持重叠采样窗口设计，在36通道交织下实现28.4dB SNDR（Nyquist频点），消除传统架构的串扰问题，属于模拟前端电路创新

Abstract

and Anantha P . Chandrakasan , Fellow, IEEE Abstract—This successive approximation register ADC uses time-interleaving to gain the energy advantage of slower cir- cuits (reduced supply voltage and improved bias points) without sacriﬁcing high speed operation. The drawbacks of interleaving are addressed through architectural solutions. Channel redun- dancy counteracts the severe yield loss that parallel circuits experience due to local variation. Clock partitioning restricts the distribution of t