← 返回 JSSC 论文列表JSSC 2008第12期Power Management90nmCharge PumpPLL
Low-Spur Low-Phase-Noise Clock Multiplier Based on a Combination of PLL and Reci
结合PLL和DLL的低杂散低相位噪声时钟乘法器
0.048 mm², 90 nm CMOS, 122 dBc/Hz @ 200 kHz offset, 800 MHz, 48 dBc reference spur, 15 mW, 1 V
电荷泵延迟锁定环锁相环相位噪声压控振荡器
▸创新点1：系统架构创新 - 结合PLL的低参考杂散和DLL的低相位噪声优势，通过双脉冲独立控制的环形振荡器设计，实现高性能时钟倍频。具体采用PLL精确设置环形延迟，同时利用DLL机制周期性重新对齐参考相位，显著提升整体性能（122 dBc/Hz相位噪声@200kHz偏移）。
▸创新点2：电路创新 - 引入自校正电荷泵技术，动态补偿上下电流失配问题。该设计通过实时校正机制消除传统电荷泵的电流不匹配误差，从而降低相位噪声和参考杂散（参考杂散低至-48 dBc）。
▸创新点3：方法创新 - 提出脉冲移除与重插入机制，消除DLL中由静态相位偏移引起的参考杂散。通过分离控制脉冲与对齐脉冲的路径，避免对齐操作对延迟控制的干扰，实现无杂散相位校准。
▸创新点4：集成创新 - 在90nm CMOS工艺下实现0.048mm²超小面积设计，同时兼顾低功耗（15mW@1V）与高性能，展示出优异的能效比与芯片面积优化能力。
Abstract
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Self-Correcting Charge Pump
Sander L. J. Gierkink , Member , IEEE
Abstract—A clock multiplier combines the low reference spur
of a PLL with the low phase noise of a recirculating DLL. It uses
a ring oscillator that has two pulses running simultaneously that
are phase independent. One pulse is used by a PLL to precisely set
ring delay while the other pulse is periodically realigned with the
reference phase by a process of pulse removal and reinsertion, sim-
ilar to a DLL. The DLL reference