A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate Y an Li, Seungpil Lee, Y upin Fong, Feng Pan, Tien-Chien Kuo, Jongmin Park, Tapan Samaddar, Hao Thai Nguyen, Man L. Mui, Khin Htoo, Teruhiko Kamei, Masaaki Higashitani, Emilio Y ero, Gyuwan Kwon, Phil Kliza, Jun Wan, Tetsuya Kaneko, Hiroshi Maejima, Hitoshi Shiga, Makoto Hamada, Norihiro Fujita, Kazunori Kanebako, Eugene Tam, Anne Koh, Iris Lu, Calvin Chia-Hong Kuo, Trung Pham, Jonathan Huynh, Qui Nguyen, Hardwell Chibvongodze, Mitsuyuki Watanabe, Ken Oowada, Grishma Shah, Byungki Woo, Ray Gao, James Chan, James Lan, Patrick Hong, Liping Peng, Debi Das, Dhritiman Ghosh, Vivek Kalluru, Sanjay Kulkarni, Raul-Adrian Cernea, Sharon Huynh

Abstract

A 16 Gb 8-level NAND flash chip on 56 nm CMOS technology has been fabricated and is being reported for the first time. This is the first 3-bit per cell (X3) chip published with All-Bitline (ABL) architecture, which doubles the write perfor- mance compared with conventional shielded bitline architecture. A new advanced cache program algorithm provides another 15% improvement in write performance. This paper also discusses a technique for resolving the sensing error resulting from CELL source line noise, which usually varies with the data pattern. The new architecture and advanced algorithm enable an 8 MB/s write performance that is comparable to previously published 2-bit per cell (4-level) NAND performance. Considering the significant cost reduction compared to 4-level NAND flash based on the same technology, this chip is a strong candidate for many mainstream applications.