JSSC 2009第1期RF & Wireless65nmPLL

A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Cl

65nm CMOS工艺多模基带处理器，支持WCDMA/HSDPA和GSM/GPRS/EDGE，采用部分时钟激活和动态地址分配降低功耗。

65nm CMOS, 33.6 mW降至19.6 mW, D1视频30fps编解码

基带处理器多模低功耗动态地址分配65nm CMOS

▸部分时钟激活方案降低音乐播放功耗

▸IP-MMU动态地址分配减少外部内存使用

▸多电源域设计降低漏电功耗

Abstract

Supporting both WCDMA with HSDPA and GSM/ GPRS/EDGE, the 9.3 9.3 mm/50SoC fabricated in triple-Vth 65nm CMOS, has three CPU cores and 20 separate power domains. Un- used power domains can be powered down to reduce the leakage power. Partial clock activation scheme especially focused on music playback scene dynamically stops a PLL and clock trees when not necessary and reduces power consumption from 33.6 mW to 19.6 mW. IP-MMU translates virtual address to physical address for 18 hardware-IPs and