A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU Masayuki Ito, Kenichi Nitta

Abstract

Supporting both WCDMA with HSDPA and GSM/ GPRS/EDGE, the 9.3 9.3 mm/50SoC fabricated in triple-Vth 65nm CMOS, has three CPU cores and 20 separate power domains. Un- used power domains can be powered down to reduce the leakage power. Partial clock activation scheme especially focused on music playback scene dynamically stops a PLL and clock trees when not necessary and reduces power consumption from 33.6 mW to 19.6 mW. IP-MMU translates virtual address to physical address for 18 hardware-IPs and virtual address space can be allocated when necessary and can be freed after its operation, reducing external memory by 43 MB. Video performance of D1 (720 520) size with 30 frames per second for MPEG/A VC decoding and encoding can be achieved under mixed virtual and physical address usage.