← 返回 JSSC 论文列表JSSC 2009第1期RF & Wireless0.13μm
Design and Optimization of an HSDPA Turbo Decoder ASIC Christian Benkeser Studen
设计并优化HSDPA Turbo解码器ASIC，实现低功耗高性能
0.13μm CMOS, 1.2 mm², 10.8 Mb/s, 32 mW
Turbo解码器HSDPA低功耗ASIC设计信道解码
▸算法级优化：通过改进Turbo解码算法，显著降低了计算复杂度和功耗，支持高达10.8 Mb/s的吞吐量，同时功耗仅为32 mW。这一优化在HSDPA标准中实现了接近香农极限的性能。
▸算术级优化：在算术运算层面进行了精细优化，减少了递归算法的计算负担，使得在0.13微米CMOS技术下，芯片面积仅为1.2 mm²（不包括焊盘），显著提高了能效比。
▸门级优化：通过门级电路设计优化，实现了高效的并行处理和低功耗操作，解决了大块尺寸和递归算法导致的流水线和并行化难题，提升了整体解码效率。
▸系统级创新：结合算法、算术和门级优化，提出了一种全面的ASIC设计方法，使得Turbo解码器在无线应用中具有更低的功耗和更小的芯片面积，满足了3G移动通信的高要求。
Abstract
eo Cupaiuolo, and
Qiuting Huang, Fellow, IEEE
Abstract—The turbo decoder is the most challenging component
in a digital HSDPA receiver in terms of computation requirement
and power consumption, where large block size and recursive algo-
rithm prevent pipelining or parallelism to be effectively deployed.
This paper addresses the complexity and power consumption
issues at algorithmic, arithmetic and gate levels of ASIC design, in
order to bring power consumption and die area of turbo decoders
to a