← 返回 JSSC 论文列表JSSC 2009第1期Clocking & PLLs65nm
Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic V ariati
65纳米工艺下实现具有时序错误检测与恢复功能的弹性电路，消除动态电压温度变化导致的时钟频率保护带
65nm CMOS, 动态电压温度变化适应, 时序错误检测与恢复
弹性电路时序错误检测亚稳态免疫动态电压调整65纳米工艺
▸动态过渡检测器与时序借用数据路径锁存器(TDTB)
▸双采样静态设计与时序借用数据路径锁存器(DSTB)
▸将亚稳态问题从数据路径和错误路径简化为仅错误路径管理
Abstract
es W . Tschanz , Member , IEEE, Nam Sung Kim, Janice C. Lee,
Chris B. Wilkerson, Shih-Lien L. Lu , Member , IEEE, Tanay Karnik , Senior Member , IEEE, and
Vivek K. De, Senior Member , IEEE
Abstract—A 65 nm resilient circuit test-chip is implemented
with timing-error detection and recovery circuits to eliminate the
clock frequency guardband from dynamic supply voltage
/40/86/67/67/41
and temperature variations as well as to exploit path-activation
probabilities for maximizing throughput. Two erro