← 返回 JSSC 论文列表JSSC 2009第2期Digital Circuits0.18μmNeural Network Accelerator
A Slew Controlled L VDS Output Driver Circuit in 0.18 /22m CMOS Technology Armin Tajalli, Student Member , IEEE, and Y
提出一种低功耗、低电压差分信号输出驱动电路，采用斜率控制技术减少阻抗失配。
0.18μm CMOS, 4.5mA, 2.5Gbps, 3.42mW/Gbps, 14.5ps抖动
低电压差分信号斜率控制低功耗阻抗匹配CMOS
▸创新点1：斜率控制技术减少阻抗失配（方法创新）。通过引入精确的斜率控制机制，有效降低了输出驱动电路与传输线之间的阻抗失配，从而减少了信号反射和抖动，实测输出抖动仅为±14.5 ps，提升了信号完整性。
▸创新点2：低功耗预驱动级设计（电路创新）。通过优化预驱动级的输入电容至50 fF，显著降低了整体功耗，同时解决了低功耗预驱动级设计中的权衡问题，实现了3.42 mW/Gbps的归一化功耗。
▸创新点3：低电压操作可行性（系统创新）。在0.18μm CMOS工艺下，通过控制电压摆幅和共模电压，使电路能够在低电源电压下稳定工作，扩展了传统工艺的应用范围。
▸创新点4：高频率操作能力（性能创新）。实测表明，该驱动电路可在高达2.5 Gbps的频率下工作，其速度仅受负载时间常数限制，展现了优异的高频性能。
Abstract
This article presents a power-efficient low-voltage differential signaling (LVDS) output driver circuit. The proposed approach helps to reduce the total input capacitance of the L VDS driver circuit and hence relaxes the tradeoffs in designing a low-power pre-driver stage. A slew control technique has also been introduced to reduce the impedance mismatch effect between the output driver circuit and the line. The pre-driver stage shows a total input capacitance of 50 fF and also controls the voltage swing and common-mode voltage at the input of the L VDS driver output stage. This makes the operation at low supply voltages using a conventional 0.18 m CMOS technology feasible. The output driver circuit consumes 4.5 mA while driving an external 100 /10 resistor with an output voltage swing of /61400 mV , achieving a normalized power dissipation of 3.42 mW/Gbps. The area of the LVDS driver circuit is 0.067 mm /50and the measured output jitter is /614.5 ps. Measurements show that the proposed L VDS driver can be used at frequencies as high as 2.5 Gbps where the speed will be limited by the load time constant.