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JSSC 2009第2期Other65nm

Analysis of the Influence of Substrate on the Performance of On-Chip MOS Decoupli

分析衬底对片上MOS去耦电容器性能的影响,提出新型六参数分析模型。
65 nm LP-CMOS, 10 MHz-10 GHz
衬底去耦电容器高频电源噪声最大导纳性能优化
新型六参数分析模型考虑衬底与器件相互作用
引入最大导纳作为去耦电容器性能的新指标
推导闭式表达式计算最大导纳
Abstract
tract—The interaction between substrate and devices is normally neglected during the design of on-chip MOS decoupling capacitors (decaps). However, it may significantly influence the decap performance to reduce high-frequency power supply noise. In this paper we propose a novel six-parameter analytical decap model which accounts for substrate and device interactions. Our model has been compared against state-of-the-art decap models. Moreover, it has been extensively validated through simulations a