← 返回 JSSC 论文列表JSSC 2009第2期Clocking & PLLs0.18μm
Design and Analysis of Actively-Deskewed Resonant Clock Networks
基于注入锁定分布式差分振荡器的自适应去偏谐振时钟网络设计,提升抖动免疫力和能效。
2-GHz, 0.18μm, >25 pF/mm²
谐振时钟网络主动去偏注入锁定抖动免疫力能效优化
▸将去偏所需的延迟线集成到注入锁定源中,显著提高抖动免疫力
▸基于谐振网格自动幅度控制的电源管理系统,提升能效
▸集成片上抖动和偏斜测量电路
Abstract
Active deskewing is an important technique for man-
aging variability in clock distributions but introduces latency and
power-supply-noise sensitivity into the resulting networks. In this
paper, an adaptively deskewed resonant clock network, based on
an injection-locked distributed differential oscillator , is described,
in which the delay lines required for deskewing are incorporated
into the injection-lock source, dramatically improving jitter immu-
nity. A power management system based on aut