← 返回 JSSC 论文列表JSSC 2009第2期Data Converters90 nmDelta-Sigma ADCDAC
Design and Measurement of a CT 16ADC With Switched-Capacitor Switched-Resistor F
提出一种改进的开关电容反馈DAC技术，降低时钟抖动敏感性和功耗。
5 mW, 312 MHz, SNR 66.4 dB, SNDR 62.4 dB, 1.92 MHz带宽
连续时间ΔΣADC开关电容DAC时钟抖动低功耗RF-CMOS
▸创新点1：提出了一种新型的开关电容与开关电阻串联（SCSR）DAC技术，通过可变串联电阻调节反馈脉冲形状，显著降低了时钟抖动对反馈脉冲宽度变化的敏感性，理论分析表明其灵敏度比传统SI RZ DAC降低30 dB。
▸创新点2：采用SCSR DAC结构有效降低了传统开关电容DAC的高输出峰值电流，从而减轻了环路滤波器积分器的压摆率要求，实测显示功耗仅为5 mW，在312 MHz工作频率下实现62.4 dB SNDR。
▸创新点3：开发了SCSR DAC的综合设计方法，通过理论建模优化开关电阻值与电容值的比例关系，在保证jitter抑制性能的同时最小化功耗和电路复杂度，适用于90 nm CMOS工艺。
▸创新点4：在二阶连续时间ΔΣ调制器中首次集成SCSR反馈DAC，系统级创新体现在1.92 MHz带宽内实现66.4 dB SNR，验证了该架构在高频应用中的可行性。
Abstract
The performance of traditional continuous-time
(CT) delta-sigma /40/1/6/41analog-to-digital converters (ADCs) is
limited by their large sensitivity to feedback pulse-width vari-
ations caused by clock jitter in their feedback digital-to-analog
converters (DACs). To mitigate that effect, we propose a mod-
ified switched-capacitor (SC) feedback DAC technique, with a
variable switched series resistor (SR). The architecture has the
additional benefit of reducing the typically high SC DAC output
peak c