JSSC 2009第2期MemoryDRAM

Fast Low Power eDRAM Hierarchical Differential Sense Ampliﬁer

提出一种用于快速低功耗eDRAM的分层差分感测放大器，具有高抗参数变化能力。

低延迟、快速恢复、短周期时间

eDRAM差分感测放大器低功耗参数变化分层结构

▸分层差分感测放大器结构：采用局部半感测放大器与全局半感测放大器通过开关连接的层次化设计，显著降低器件参数变异对性能的影响，提升信号差分幅度（方法创新）。

▸短局部位线设计：通过缩短局部位线长度，减少寄生电容和电阻，从而加快信号传输速度并降低功耗（电路创新）。

▸Vdd/2感测电压降低静态功耗：采用近似Vdd/2的感测电压，有效减少局部和全局感测放大器的漏电流，显著降低静态功耗（电路创新）。

▸快速恢复与低延迟：通过优化的时钟与时序设计，实现快速数据恢复和低操作延迟，适用于高频应用（系统创新）。

Abstract

In this paper , a hierarchical differential sense ampli- ﬁer for fast, low power DRAM arrays in logic-based eDRAM tech- nology that operates with large parameter variations is described. Unique features of the hierarchical sense ampliﬁer include its short local bit lines and a local half sense ampliﬁer p device latch that is connected by a switch to a global half sense ampliﬁer n device latch. When the local and global half latches are connected by the switch, they form a conventional cross-coupled latch. As a result of the short bit lines, the magnitude of the differential signal is large enough to overcome device variations in the various pairs of like-devices of the sense ampliﬁer. The differential sense ampliﬁer is quite insensitive to absolute parameter variation and mainly sen- sitive to mismatches between paired devices. The hierarchical dif- ferential sense ampliﬁer has very low static power due to the use of a sense voltage of approximately Vdd/2 which causes low leakage in the local and global sense ampliﬁers as well as in the storage cell. Low active power also results from this Vdd/2 sensing. In addition, simulation results show low latency, fast restore, and fast cycle time with clocking and timing that are relatively simple.