JSSC 2009第2期Clocking & PLLs0.13μmPLLClock Generation

Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers

提出一种基于LC-VCO的PLL频率合成器，通过环路带宽跟踪技术实现恒定带宽。

0.13μm CMOS, 3.1-3.9GHz, <4%带宽变化

LC-VCOPLL频率合成器环路带宽CMOS

▸采用平均变容二极管的分裂调谐LC-VCO

▸伺服环路设置电荷泵电流与振荡频率平方成反比

▸结合上述技术实现宽频率范围内恒定环路带宽

Abstract

, IEEE, Kartikeya Mayaram , Fellow, IEEE, and Un-Ku Moon, Fellow, IEEE Abstract—An LC-VCO based phase-locked loop (PLL) fre- quency synthesizer which incorporates loop bandwidth tracking is described. In order to minimize loop bandwidth variations resulting from changes in the LC-VCO gain, the proposed PLL employs an averaging varactor based split-tuned LC-VCO and a servo loop which sets the charge-pump current to be inversely proportional to the square of the oscillation frequency. The com- bi