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A 10-bit 50 MSs Pipelined ADC With Capacitor-Sharing and Variable-103109Opamp By
提出一种低功耗、小面积的10位50 MS/s流水线ADC，采用电容共享和可变增益运放技术。
10-bit, 50 MS/s, 12 mW, 1.8 V
电容共享低功耗运放共享流水线ADC小面积
▸创新点1：去除前端采样保持放大器（SHA）的系统创新。通过消除传统ADC中的SHA模块，显著降低了功耗和芯片面积，同时通过提出的误差补偿技术解决了因去除SHA导致的采样误差问题，实现了10位分辨率。
▸创新点2：运放共享技术的电路创新。在两个连续的流水线级之间共享一个运放，减少了运放数量（仅需两个运放），从而大幅降低功耗和面积，同时通过优化时序和反馈技术抑制了运放共享带来的记忆效应。
▸创新点3：电容共享技术的电路创新。通过复用电容网络，进一步减少了芯片面积和功耗，同时结合动态电容匹配技术，确保了10位精度的线性度（DNL<0.39 LSB, INL<0.81 LSB）。
▸创新点4：可变跨导运放（Variable-gm Opamp）的电路创新。根据流水线级的需求动态调整运放跨导，优化了功耗效率（总功耗12 mW@1.8V），同时支持50 MS/s采样率下的高动态性能（SNDR=56.2 dB, SFDR=72.7 dB）。
Abstract
, Member , IEEE
Abstract—A pipelined analog-to-digital converter (ADC) ar-
chitecture which is suitable for low power and small area is
presented. The prototype ADC achieves 10-bit resolution with
only two opamps by removing a front-end sample-and-hold ampli-
fier (SHA) and sharing an opamp between two successive pipeline
stages. The errors from the absence of SHA and opamp-sharing
are greatly reduced by the proposed techniques and circuits.
Further reduction of power and area is achieved by usin