JSSC 2009第3期Clocking & PLLs90nmVCONeural Network Accelerator

A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology Lan-Chou Cho, Chihun Lee, Chao-Ching Hung

本文提出了一种33.6-33.8 Gb/s突发模式时钟数据恢复电路，采用90 nm CMOS工艺实现。

90 nm CMOS, 1.2V, 33.72 Gb/s, 7.56 ps峰峰值抖动, 1.15 ps均方根抖动, 73 mW功耗

突发模式时钟数据恢复LC门控压控振荡器宽带输入匹配电路相位选择器90 nm CMOS

▸LC门控压控振荡器减少数据抖动

▸宽带输入匹配电路接收宽带数据

▸相位选择器克服全速率操作中的假锁相

Abstract

A 33.6–33.8 Gb/s burst-mode clock/data recovery circuit (BMCDR) is presented in this paper. T o reduce the data jitter and generate the high-frequency output clock, the LC gated voltage-controlled oscillator is presented. T o receive and transmit the broadband data, a wideband input matching circuit and a wideband data buffer are presented, respectively. The phase selector is proposed to overcome the false phase lock due to the full-rate operation. This proposed BMCDR has been fabricated in a 90 nm CMOS process. The measured peak-to-peak and rms jitters for the recovered data are 7.56 ps and 1.15 ps, respectively, for a 33.72 Gb/s, 2 /49/49 1 PRBS. The measured bit error rate is less than /49/48 /56for a 33.72 Gb/s, 2 /55 1 PRBS. It consumes 73 mW without buffers from a 1.2 V supply.