← 返回 JSSC 论文列表JSSC 2009第3期RF & Wireless0.13微米Pipeline ADCTime-Interleaved ADC
A 48 GSs 5-bit ADC-Based Receiver With Embedded DFE for Signal Equalization Aida
设计了一款5位4.8 GS/s 4路时间交织ADC，采用0.13微米CMOS技术，用于接收器前端。
5-bit, 4.8 GS/s, 30.4 dB SNDR, 300 mW功耗, 1.2-V电源
ADCDFE数字参考校准时间交织流水线
▸时间交织ADC使用前瞻流水线级以提高采样率和线性残留特性
▸电容预充电技术减少不完全稳定残留的记忆效应误差至2%
▸采用逐级反馈补偿系统可能的带宽限制
Abstract
ang , Senior Member , IEEE
Abstract—A 5-bit 4.8 GS/s 4-way time-interleaved ADC is de-
signed for a receiver front-end in a 0.13
m CMOS technology.
Each time-interleaved ADC uses look-ahead pipelined stages to en-
able higher sample rates and more linear residue characteristics
than a conventional pipeline ADC. At 1.2 GHz per path, the residue
amplifiers settle to 75% of their final value, however, the linear
residue characteristics allows using digital reference calibration to
enable 30.4 dB of