Abstract
This paper describes the design and performance of a 90 nm CMOS SA W-less receiver with DigRF interface that sup- ports 10 WCDMA bands (I, II, III, IV , V , VI, VIII, IX, X, XI) and 4 GSM bands (GSM850, EGSM900, DCS1800, PCS1900). The re- ceiver is part of a single-chip SA W-less transceiver reference plat- form IC for mass-market smartphones, which has been designed to meet Category 10 HSDPA (High Speed Downlink Packet Ac- cess) requirements. The novel receiver core consists of a single- stage transconductance amplifier (TCA) with large gain control range, a current commutating passive mixer enhanced for auto- matic on chip IIP2 calibration with 25% duty-cycle LO injection and threshold adjust, and current-input complex Direct Coupled Filter (DCF). The low noise TCAs are designed without inductive loads to save area. A self-contained on chip automatic IIP2 cali- bration system with algorithm routine, implemented in firmware, is used to optimize IIP2 performance. This topology eliminates the external LNA, inter-stage SA W filter and transimpedance ampli- fier (TZA) in conventional WCDMA designs and results in cur- rent drain and die area savings as well as improved noise. The 25% duty-cycle LO injection, with threshold adjustment, into a current driven passive double-balanced mixer results in 3 dB ad- ditional gain, lower noise figure and lower intermodulation distor- tion. Large signal blocking and 1/f noise performance are improved significantly by eliminating the 0 and 180 LO si