← 返回 JSSC 论文列表JSSC 2009第3期Clocking & PLLs0.13μmNeural Network Accelerator
An LC-Based Clock Buffer With Tunable Injection Locking Li-Min Lee Member IEEE
提出一种基于LC的可调注入锁定时钟缓冲器，通过混合两种拓扑结构自适应调整比例以最小化抖动。
1.2-V 0.13-μm CMOS, 12 mW功耗
时钟分配注入锁定振荡器抖动LC谐振缓冲器谐振时钟
▸混合两种LC拓扑结构的时钟缓冲器设计
▸自适应调整比例以优化抖动
▸基于电压摆幅数字化的频率调谐技术
Abstract
t—This paper introduces a hybridized version of two
common topologies of LC-based clock buffers. The proposed
design can minimize jitter by adaptively adjusting the ratio be-
tween these two topologies. The analysis shows that the setting
for optimum jitter depends on the relative level between the input
noise and the inherent noise of the clock buffer. The long-term
and short-term jitters are both studied and supported by mea-
surement. A frequency tuning technique based on a voltage-swing
digi