JSSC 2009第3期Memorysub-90nmSRAM

Design of Sub-90 nm Low-Power and V ariation Tolerant PD/SOI SRAM Cell Based on Dynamic

研究90纳米以下低功耗和抗变异的PDSOI SRAM单元设计，分析浮体效应和泄漏对稳定性的影响。

sub-90nm SOI, 高阈值电压, 厚氧化层

SRAM浮体效应低功耗抗变异SOI

▸首次研究了浮体效应对SRAM单元读写稳定性的影响

▸提出使用高阈值电压和厚氧化层晶体管改善泄漏和稳定性

▸在90纳米以下SOI技术中验证了设计的有效性

Abstract

IEEE, Saibal Mukhopadhyay , Member , IEEE, Donald W. Plass, Y uen H. Chan, Ching-Te Chuang, Fellow, IEEE, and Y ue Tan Abstract—In this paper we have studied the impacts of ﬂoating body effect, device leakage, and gate oxide tunneling leakage on the read and write-ability of a PD/SOI CMOS SRAM cell under Vt, L and W variations in sub-100 nm technology for the ﬁrst time. The ﬂoating body effect is shown to degrade the read stability while improving the write-ability. On the other hand, the gate-