JSSC 2009第3期Other130nm

Low-Power Race-Free Programmable Logic Arrays Giby Samson Student Member IEEE a

提出一种低功耗无竞争可编程逻辑阵列（PLA）设计，采用动态NAND门实现AND平面，动态NOR门实现OR平面，显著降低功耗并消除时序竞争。

130nm工艺, 1.61GHz最大工作频率, 能耗延迟积降低43%

可编程逻辑阵列低功耗动态逻辑时序竞争能耗延迟积

▸创新点1：采用动态NAND门实现AND平面，通过分层组合动态NAND门结构替代传统动态NOR门，显著降低功耗（43%能量延迟积优化），属于电路创新。

▸创新点2：保留动态NOR门实现OR平面，维持传统PLA的高速特性，同时与NAND结构协同消除时序竞争，属于系统级架构创新。

▸创新点3：完全消除AND/OR平面间的关键时序竞争，通过NAND-NOR组合避免预充电-求值阶段的信号冲突，提升工艺波动下的电路鲁棒性，属于时序设计方法创新。

▸创新点4：在130nm低待机功耗工艺上验证1.61GHz最高工作频率，实测硅片功能完整性，提供可量产的可靠性数据支撑，属于验证创新。

Abstract

tract—Conventional programmable logic arrays (PLAs) im- plement both the AND and OR logic planes with dynamic NOR gates. They are fast, regular in structure and easy to program. However , they have high power dissipation and suffer from an in- herent timing race that increases design effort, reduces circuit ro- bustness in the presence of variations, and adversely impacts per- formance. In this paper, a PLA which implements the AND plane as a hierarchical combination of dynamic NAND gates and re