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A 1.2-V 250-mW 14-b 100-MS/s Digitally Calibrated Pipeline ADC in 90-nm CMOS Hans V an de V el, Member , IEEE, Berry A. J. Buter, Hendrik van der Ploeg, Maarten V ertregt , Member , IEEE, Govert J. G. M. Geelen , Member , IEEE, and Edward J. F. Paulus
90纳米CMOS工艺下实现的14位100MS/s数字校准流水线ADC，功耗250mW
14位分辨率, 100MS/s采样率, 73dB SNR, 90dB SFDR, 250mW功耗
流水线ADC数字校准CMOS低功耗高分辨率
▸数字背景校准算法降低线性要求
▸第一级流水线范围缩放实现最大信号摆幅
▸电荷复位开关消除ISI引起的失真
Abstract
This paper describes a digitally calibrated pipeline analog-to-digital converter (ADC) implemented in 90 nm CMOS technology with a 1.2 V supply voltage. A digital background cal- ibration algorithm reduces the linearity requirements in the first stage of the pipeline chain. Range scaling in the first pipeline stage enables a maximal 1.6 /86/112/112input signal swing, and a charge-reset switch eliminates ISI-induced distortion. The 14b ADC achieves 73 dB SNR and 90 dB SFDR at 100 MS/s sampling rate and 250 mW power consumption. The 73 dB SNDR performance is maintained within 3 dB up to a Nyquist input frequency and the FOM is 0.68 pJ per conversion-step.