← 返回 JSSC 论文列表JSSC 2009第4期Clocking & PLLs45nmClock GenerationDRAM
A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS Peter J. Klim , Member , IEEE
一款采用45nm SOI CMOS工艺的1MB缓存子系统原型，集成2GHz eDRAM宏单元，具有18ns访问延迟。
45nm SOI CMOS, 2GHz eDRAM, 1.8ns latency
缓存子系统嵌入式DRAMSOI CMOS可编程流水线并发刷新
▸集成2GHz嵌入式DRAM（eDRAM）宏单元
▸采用可编程流水线技术实现1.8ns延迟
▸具备并发刷新功能
Abstract
We describe a single voltage supply, 1 MB cache sub- system prototype that integrates 2 GHz embedded DRAM (eDRAM) macros with on-chip word-line voltage supply generation, a 4 Kb one-time-programmable read-only memory (OTPROM) for redundancy and repair control, on-chip OTPROM programming voltage generation, clock generation and distri- bution, array built-in self-test circuitry (ABIST), user logic and pervasive logic. The eDRAM employs a programmable pipeline, achieving 1.8 ns latency, and features concurrent refresh capability.