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Next Generation Intel Core Micro-Architecture Nehalem Clocking Nasser Kurd Membe
本文介绍了英特尔Nehalem微架构的核心和I/O时钟架构，采用45nm工艺，优化了时钟性能和功耗。
45nm工艺, 25.6 GB/s QuickPath带宽, 32 GB/s DDR3流量
Nehalem微架构PLLDLLQuickPathDDR3
▸本地PLL布局实现模块化和高效扩展
▸快速锁定、低偏移PLL减少锁定时间56%
▸自适应频率和占空比机制提升核心频率5%
Abstract
d , Member , IEEE, Jonathan Douglas, and
Rajesh Kumar
Abstract—This paper describes the core and I/O clocking archi-
tecture of the next generation Intel ® Core™ micro-architecture
processor (Nehalem), designed on a 45 nm process technology.
Local PLL placement provides modularity and power-efficient
scalability by allowing independent frequency and voltage do-
mains. Fast-locking, low-skew PLLs are used to achieve 56% lock
time reduction and 30% long-tem jitter improvement. Adaptive
frequency, s