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JSSC 2009第4期Memorysub-30 nmFlash Memory

Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-

通过NAND闪存与控制器的协同设计，实现低功耗高速SSD
功耗降低60%，速度提升150%
NAND闪存SSD低功耗设计高速存储协同设计
▸选择性位线预充电方案：通过消除验证读取阶段不必要的位线预充电，显著降低功耗23%。该方法属于电路创新，优化了NAND闪存的读取操作流程，减少了能量浪费。
▸先进源线编程方案：采用分层源线结构，在不增加芯片面积的情况下，将编程脉冲期间的负载电容降低90%，功耗减少48%。这是电路架构创新，改进了编程效率。
▸智能交错技术：通过抑制电流峰值，实现NAND闪存的高速并行写入操作，使SSD速度提升150%。属于系统级创新，优化了控制器与存储芯片的协同工作模式。
Abstract
D) Ken Takeuchi, Member , IEEE Abstract—As the cell size of the NAND flash memory has been scaled down by 40%–50% per year and the memory capacity has been doubling every year, a solid-state drive (SSD) that uses NAND as mass storage for personal computers and enterprise servers is attracting much attention. To realize a low-power high-speed SSD, the co-design of NAND flash memory and NAND controller cir- cuits is essential. In this paper , three new circuit technologies, the selective bit-line pr