▸WLUD电路创新：通过字线欠驱动（WLUD）技术解决DNF SRAM单元读取稳定性问题，采用动态电压调节机制，在45nm工艺下实现20%的电压容差，显著提升工艺温度和电源噪声容忍度（方法创新）
▸DVC方案创新：动态电压崩溃（DVC）技术通过动态调整单元保持电压与写入电压的比值，在低压环境下以牺牲部分保持裕度为代价，换取写入稳定性的显著提升（电路创新）
▸P-cell结构创新：采用pMOS传输管和预充电位线设计，通过无扩散凹槽的nMOS下拉管尺寸优化实现固有比率化读取，相比传统单元提升15%的读取裕度（器件创新）
▸系统级协同优化：联合WLUD与DVC技术，在测试芯片中验证了M-cell在0.9-1.3V宽电压范围内的稳定工作，同时P-cell通过pMOS强度、nMOS尺寸和DVC参数的协同设计获得低压工作窗口（系统创新）
Abstract
Multi-Vcc Circuits
Muhammad Khellah, Member , IEEE, Nam Sung Kim , Senior Member , IEEE , Yibin Ye,
Dinesh Somasekhar, Member , IEEE, Tanay Karnik , Senior Member , IEEE , Nitin Borkar,
Gunjan Pandya, Member , IEEE, Fatih Hamzaoglu , Member , IEEE, Tom Coan, Yih Wang , Member , IEEE,
Kevin Zhang, Senior Member , IEEE, Clair Webb , Member , IEEE, and Vivek De , Senior Member , IEEE
Abstract—This paper addresses the stability problem of diffu-
sion-notch-free (DNF) SRAM cells used in dense last l