← 返回 JSSC 论文列表JSSC 2009第5期Clocking & PLLs0.13μmDLLDRAM
A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM
一种采用抖动抑制技术的DLL，用于DRAM，在噪声环境下降低输出抖动。
1 GHz输出时钟，4.58 ps RMS抖动，29 ps峰峰值抖动
DLL抖动抑制DRAM相位误差CMOS
▸通过监测输入抖动幅度控制环路响应模式
▸调整相位误差跟踪概率
▸降低有效输入相位误差方差和窄化有效环路带宽
Abstract
A DLL featuring jitter reduction techniques for
a noisy environment is described. It controls a loop response
mode by monitoring the magnitude of input jitter caused by
supply noise. This technique varies the probability of phase error
tracking. It reduces the output jitter of the DLL due to a low
effective variance of input phase error and a narrow effective loop
bandwidth. The DLL is implemented in a 0.13
m CMOS process.
Under noisy environments, the output clock of 1 GHz has 4.58 ps
RMS and 2