← 返回 JSSC 论文列表JSSC 2009第5期RF & Wireless0.13μmCDRHigh-Speed Link
A Fully Integrated 013- 22m CMOS 40-Gbs Serial Link Transceiver Jeong-Kyoum Kim
本文介绍了一种基于0.13μm CMOS工艺的全集成40Gb/s串行链路收发器。
0.13μm CMOS, 1.45V, 40Gb/s, 3.6W, 3.4×2.9mm²
串行链路收发器CMOS时钟数据恢复线性均衡器
▸使用脉冲锁存器和电感峰值技术实现10mV灵敏度
▸直接对VCO进行比例控制以减少反馈延迟
▸线性均衡器提升39Gb/s下的眼图开口度20%
Abstract
EE, Gyudong Kim , Member , IEEE, and
Deog-Kyoon Jeong, Member , IEEE
Abstract—A fully integrated 40-Gb/s transceiver fabricated in
a 0.13-
m CMOS technology is presented. The receiver operates
at a 20-GHz clock performing half-rate clock and data recovery.
Despite the low
/102/84of 70 GHz, the input sampler achieves 10-mV
sensitivity using pulsed latches and inductive-peaking techniques.
In order to minimize the feedback latency in the bang-bang con-
trolled CDR loop, the proportional control i